0.18μm CMOS process highly sensitive differential optically reconfigurable gate array VLSI

Takahiro Watanabe; Minoru Watanabe

doi:10.1109/ISVLSI.2012.71

0.18μm CMOS process highly sensitive differential optically reconfigurable gate array VLSI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Currently, demand is increasing for high-speed dynamic reconfiguration on programmable devices to improve their performance. To support high-speed dynamic reconfiguration, optically reconfigurable gate arrays (ORGAs) have been undergoing rapid development. Moreover, to more increase the reconfiguration speed, optically differential reconfigurable gate arrays (ODRGAs) incorporating a differential reconfiguration method between configuration contexts have been developed. An ODRGA comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. Its large-bandwidth optical connection enables high-speed reconfiguration. However, photodiode sensitivities of conventional ODRGAs are not good. This paper therefore presents a newly fabricated 0.18 um CMOS process optically differential reconfigurable gate array VLSI chip with highly sensitive photo-circuits.

Original language	English
Title of host publication	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Pages	308-313
Number of pages	6
DOIs	https://doi.org/10.1109/ISVLSI.2012.71
Publication status	Published - 2012
Externally published	Yes
Event	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012 - Amherst, MA, United States Duration: Aug 19 2012 → Aug 21 2012

Publication series

Name	Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012

Conference

Conference	2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012
Country/Territory	United States
City	Amherst, MA
Period	8/19/12 → 8/21/12

Keywords

Field Programmable Gate Arrays
Holographic memory
Optically reconfigurable gate arrays

ASJC Scopus subject areas

Control and Systems Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/ISVLSI.2012.71

Cite this

0.18μm CMOS process highly sensitive differential optically reconfigurable gate array VLSI. / Watanabe, Takahiro; Watanabe, Minoru.
Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012. 2012. p. 308-313 6296491 (Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Watanabe, T & Watanabe, M 2012, 0.18μm CMOS process highly sensitive differential optically reconfigurable gate array VLSI. in Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012., 6296491, Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, pp. 308-313, 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, United States, 8/19/12. https://doi.org/10.1109/ISVLSI.2012.71

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0.18μm CMOS process highly sensitive differential optically reconfigurable gate array VLSI

Abstract

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Keywords

ASJC Scopus subject areas

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