100-Mbit/s single-chip Q-VLMS MLSE equalizer LSI for TDMA mobile radio communications

Yushi Shirato, Kiyoshi Kobayashi, Satoshi Denno

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


A single-chip 100-Mbit/s burst-operation two-tap maximum likelihood sequence estimation (MLSE) equalizer LSI for QPSK signals is introduced. It also supports two-branch diversity combining. Three new techniques are used to realize this fast equalizer LSI: the quantized variable-gain least mean squares (VLMS) algorithm, which has small processing delay with fast convergence characteristics; a simple complex-valued multiplication scheme based on inverting the sign and switching the in-phase and quadrature-phase components; and a parallel structure to minimize the processing delay of path memory. The chip, containing 75 kgates, is manufactured using the 0.45-μm-CMOS gate array process. The supply voltage is 3.3 V. This LSI offers higher processing speed than any other conventional equalizer chip for mobile radio communications.

Original languageEnglish
Pages (from-to)1178-1185
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Issue number8
Publication statusPublished - Aug 2001
Externally publishedYes


  • Burst operation
  • CMOS gate array
  • Frequency-selective fading
  • LSI
  • MLSE equalizer
  • QPSK scheme
  • VLMS algorithm
  • Wide-band mobile radio communication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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