A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

Minoru Watanabe; Fuminori Kobayashi

doi:10.1109/ASPDAC.2007.357972

A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 μm - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages	124-125
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2007.357972
Publication status	Published - 2007
Externally published	Yes
Event	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan Duration: Jan 23 2007 → Jan 27 2007

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Country/Territory	Japan
City	Yokohama
Period	1/23/07 → 1/27/07

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2007.357972

Cite this

Watanabe, M., & Kobayashi, F. (2007). A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 124-125). Article 4196018 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2007.357972

A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. / Watanabe, Minoru; Kobayashi, Fuminori.
Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 124-125 4196018 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Watanabe, M & Kobayashi, F 2007, A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. in Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007., 4196018, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 124-125, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 1/23/07. https://doi.org/10.1109/ASPDAC.2007.357972

@inproceedings{c8ed1946758949aaa9a46d456658a571,

title = "A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI",

abstract = "A Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 μm - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.",

author = "Minoru Watanabe and Fuminori Kobayashi",

year = "2007",

doi = "10.1109/ASPDAC.2007.357972",

language = "English",

isbn = "1424406293",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "124--125",

booktitle = "Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007",

note = "ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 ; Conference date: 23-01-2007 Through 27-01-2007",

}

TY - GEN

T1 - A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

AU - Watanabe, Minoru

AU - Kobayashi, Fuminori

PY - 2007

Y1 - 2007

N2 - A Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 μm - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.

AB - A Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 μm - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.

UR - http://www.scopus.com/inward/record.url?scp=46649118075&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=46649118075&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2007.357972

DO - 10.1109/ASPDAC.2007.357972

M3 - Conference contribution

AN - SCOPUS:46649118075

SN - 1424406293

SN - 9781424406296

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 124

EP - 125

BT - Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007

T2 - ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007

Y2 - 23 January 2007 through 27 January 2007

ER -

A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

Abstract

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