A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology

Minoru Watanabe; Fuminori Kobayashi

doi:10.1145/1118299.1118330

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2006
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2006
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	108-109
Number of pages	2
ISBN (Print)	0780394518, 9780780394513
DOIs	https://doi.org/10.1145/1118299.1118330
Publication status	Published - 2006
Externally published	Yes
Event	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan Duration: Jan 24 2006 → Jan 27 2006

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2006

Conference

Conference	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Country/Territory	Japan
City	Yokohama
Period	1/24/06 → 1/27/06

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1145/1118299.1118330

Cite this

Watanabe, M., & Kobayashi, F. (2006). A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 108-109). Article 1594660 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1118299.1118330

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology. / Watanabe, Minoru; Kobayashi, Fuminori.
Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., 2006. p. 108-109 1594660 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Watanabe, M & Kobayashi, F 2006, A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology. in Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006., 1594660, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2006, Institute of Electrical and Electronics Engineers Inc., pp. 108-109, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, Yokohama, Japan, 1/24/06. https://doi.org/10.1145/1118299.1118330

Watanabe M, Kobayashi F. A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc. 2006. p. 108-109. 1594660. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/1118299.1118330

Watanabe, Minoru ; Kobayashi, Fuminori. / A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology. Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. Institute of Electrical and Electronics Engineers Inc., 2006. pp. 108-109 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

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A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μm CMOS technology

Publication series

Conference

ASJC Scopus subject areas

Access to Document

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Cite this