A dynamic Optically Reconfigurable gate array using dynamic method

Minoru Watanabe; Fuminori Kobayashi

A dynamic Optically Reconfigurable gate array using dynamic method

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

To date, we have fabricated 68-gate-count Dynamic Optically Reconfigurable Gate Arrays (DORGAs). Their reconfiguration period has been confirmed as less than 6 ns. As the next step, we have begun development of high-gate-count DORGAs. The new DORGA-VLSI chip can achieve a 26,350-gate count through reduction of the photodiode size, photodiode spacing, and through introduction of a small dynamic optical reconfiguration circuit. This paper presents the new design of that 26,350-gate-count DORGA using a standard 0.35um 3-Metal CMOS process technology. In addition, photodiode characteristics are extracted from experimental results using an estimation chip with similar photodiodes and an identical gate array structure.

Original language	English
Title of host publication	ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005
Pages	50-58
Number of pages	9
Publication status	Published - 2005
Externally published	Yes
Event	International Workshop on Applied Reconfigurable Computing 2005, ARC 2005 - Algarve, Portugal Duration: Feb 22 2005 → Feb 23 2005

Publication series

Name	ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005

Conference

Conference	International Workshop on Applied Reconfigurable Computing 2005, ARC 2005
Country/Territory	Portugal
City	Algarve
Period	2/22/05 → 2/23/05

Keywords

Dynamically reconfigurable processors
FPGAs
Optical reconfiguration
Optically reconfigurable devices

ASJC Scopus subject areas

Computational Theory and Mathematics
Applied Mathematics

Cite this

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title = "A dynamic Optically Reconfigurable gate array using dynamic method",

abstract = "To date, we have fabricated 68-gate-count Dynamic Optically Reconfigurable Gate Arrays (DORGAs). Their reconfiguration period has been confirmed as less than 6 ns. As the next step, we have begun development of high-gate-count DORGAs. The new DORGA-VLSI chip can achieve a 26,350-gate count through reduction of the photodiode size, photodiode spacing, and through introduction of a small dynamic optical reconfiguration circuit. This paper presents the new design of that 26,350-gate-count DORGA using a standard 0.35um 3-Metal CMOS process technology. In addition, photodiode characteristics are extracted from experimental results using an estimation chip with similar photodiodes and an identical gate array structure.",

keywords = "Dynamically reconfigurable processors, FPGAs, Optical reconfiguration, Optically reconfigurable devices",

author = "Minoru Watanabe and Fuminori Kobayashi",

year = "2005",

language = "English",

isbn = "9729935386",

series = "ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005",

pages = "50--58",

booktitle = "ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005",

note = "International Workshop on Applied Reconfigurable Computing 2005, ARC 2005 ; Conference date: 22-02-2005 Through 23-02-2005",

}

TY - GEN

T1 - A dynamic Optically Reconfigurable gate array using dynamic method

AU - Watanabe, Minoru

AU - Kobayashi, Fuminori

PY - 2005

Y1 - 2005

N2 - To date, we have fabricated 68-gate-count Dynamic Optically Reconfigurable Gate Arrays (DORGAs). Their reconfiguration period has been confirmed as less than 6 ns. As the next step, we have begun development of high-gate-count DORGAs. The new DORGA-VLSI chip can achieve a 26,350-gate count through reduction of the photodiode size, photodiode spacing, and through introduction of a small dynamic optical reconfiguration circuit. This paper presents the new design of that 26,350-gate-count DORGA using a standard 0.35um 3-Metal CMOS process technology. In addition, photodiode characteristics are extracted from experimental results using an estimation chip with similar photodiodes and an identical gate array structure.

AB - To date, we have fabricated 68-gate-count Dynamic Optically Reconfigurable Gate Arrays (DORGAs). Their reconfiguration period has been confirmed as less than 6 ns. As the next step, we have begun development of high-gate-count DORGAs. The new DORGA-VLSI chip can achieve a 26,350-gate count through reduction of the photodiode size, photodiode spacing, and through introduction of a small dynamic optical reconfiguration circuit. This paper presents the new design of that 26,350-gate-count DORGA using a standard 0.35um 3-Metal CMOS process technology. In addition, photodiode characteristics are extracted from experimental results using an estimation chip with similar photodiodes and an identical gate array structure.

KW - Dynamically reconfigurable processors

KW - FPGAs

KW - Optical reconfiguration

KW - Optically reconfigurable devices

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M3 - Conference contribution

AN - SCOPUS:26844569350

SN - 9729935386

SN - 9789729935381

T3 - ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005

SP - 50

EP - 58

BT - ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005

T2 - International Workshop on Applied Reconfigurable Computing 2005, ARC 2005

Y2 - 22 February 2005 through 23 February 2005

ER -

A dynamic Optically Reconfigurable gate array using dynamic method

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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