TY - GEN
T1 - A uniform partitioning method for mono-instruction set computer (MISC)
AU - Ito, Hiroyuki
AU - Watanabe, Minoru
PY - 2012
Y1 - 2012
N2 - As gates in field programmable gate arrays (FPGAs) become usable in ever-increasing numbers, FPGAs are becoming more widely applied in various embedded systems. FPGAs have been demonstrated as useful renewable devices. Recently however, a hard-core processor inside an FPGA is frequently used for high-performance systems so that the implementation of the hard-core processor decreases the possibility of a specification change and reuse of its FPGA. Therefore, demand for implementing a soft-core processor onto an FPGA is gaining. In response to that demand, FPGA vendors have provided soft-core processors for FPGAs, but those processors invariably provide lower performance than hard-core processors do. Therefore, this paper presents high-performance mono-instruction set computer (MISC) architecture that fully exploits the programmability of a dynamically reconfigurable fine-grained gate array. In addition, this paper presents a proposal of a uniform partitioning method for the MISC architecture.
AB - As gates in field programmable gate arrays (FPGAs) become usable in ever-increasing numbers, FPGAs are becoming more widely applied in various embedded systems. FPGAs have been demonstrated as useful renewable devices. Recently however, a hard-core processor inside an FPGA is frequently used for high-performance systems so that the implementation of the hard-core processor decreases the possibility of a specification change and reuse of its FPGA. Therefore, demand for implementing a soft-core processor onto an FPGA is gaining. In response to that demand, FPGA vendors have provided soft-core processors for FPGAs, but those processors invariably provide lower performance than hard-core processors do. Therefore, this paper presents high-performance mono-instruction set computer (MISC) architecture that fully exploits the programmability of a dynamically reconfigurable fine-grained gate array. In addition, this paper presents a proposal of a uniform partitioning method for the MISC architecture.
KW - CISCs
KW - FPGAs
KW - Mono-instruction set computers
KW - ORGAs
KW - RISCs
UR - http://www.scopus.com/inward/record.url?scp=84870769457&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84870769457&partnerID=8YFLogxK
U2 - 10.1109/NBiS.2012.107
DO - 10.1109/NBiS.2012.107
M3 - Conference contribution
AN - SCOPUS:84870769457
SN - 9780769547794
T3 - Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012
SP - 832
EP - 837
BT - Proceedings of the 2012 15th International Conference on Network-Based Information Systems, NBIS 2012
T2 - 2012 15th International Conference on Network-Based Information Systems, NBIS 2012
Y2 - 26 September 2012 through 28 September 2012
ER -
