An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture

Daisaku Seto; Minoru Watanabe

doi:10.1109/ASPDAC.2009.4796460

An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on the use of junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm² and a 0.35 μm-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper shows an experimental result of a long retention time of its photodiode memory architecture.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2009
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2009
Pages	117-118
Number of pages	2
DOIs	https://doi.org/10.1109/ASPDAC.2009.4796460
Publication status	Published - 2009
Externally published	Yes
Event	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan Duration: Jan 19 2009 → Jan 22 2009

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Country/Territory	Japan
City	Yokohama
Period	1/19/09 → 1/22/09

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2009.4796460

Cite this

Seto, D., & Watanabe, M. (2009). An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. In Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009 (pp. 117-118). Article 4796460 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2009.4796460

An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. / Seto, Daisaku; Watanabe, Minoru.
Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. 2009. p. 117-118 4796460 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Seto, D & Watanabe, M 2009, An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. in Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009., 4796460, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 117-118, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, Japan, 1/19/09. https://doi.org/10.1109/ASPDAC.2009.4796460

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An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture

Abstract

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ASJC Scopus subject areas

Access to Document

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