An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

Minoru Watanabe

doi:10.1109/SOCC.2007.4545430

An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A zero-overhead dynamic optically reconfigurable gate array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize both a high gate-count and zero-overhead rapid reconfiguration. This paper presents the world's largest 11,424 gate-count zero-overhead VLSI chip fabricated on a 96.04 mm² chip using 0.35 μm-3 metal CMOS process technology. The optical reconfiguration circuit, the gate array structure, the CAD layout, and the performance of ZO-DORGA-VLSI are described, with reference to experimental results related to the reconfiguration period and retention time.

Original language	English
Title of host publication	Proceedings - 20th Anniversary IEEE International SOC Conference
Pages	75-78
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2007.4545430
Publication status	Published - 2007
Externally published	Yes
Event	20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan, Province of China Duration: Sept 26 2007 → Sept 29 2007

Publication series

Name	Proceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference	20th Anniversary IEEE International SOC Conference
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	9/26/07 → 9/29/07

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/SOCC.2007.4545430

Cite this

Watanabe, M 2007, An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. in Proceedings - 20th Anniversary IEEE International SOC Conference., 4545430, Proceedings - 20th Anniversary IEEE International SOC Conference, pp. 75-78, 20th Anniversary IEEE International SOC Conference, Hsinchu, Taiwan, Province of China, 9/26/07. https://doi.org/10.1109/SOCC.2007.4545430

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abstract = "A zero-overhead dynamic optically reconfigurable gate array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize both a high gate-count and zero-overhead rapid reconfiguration. This paper presents the world's largest 11,424 gate-count zero-overhead VLSI chip fabricated on a 96.04 mm2 chip using 0.35 μm-3 metal CMOS process technology. The optical reconfiguration circuit, the gate array structure, the CAD layout, and the performance of ZO-DORGA-VLSI are described, with reference to experimental results related to the reconfiguration period and retention time.",

author = "Minoru Watanabe",

year = "2007",

doi = "10.1109/SOCC.2007.4545430",

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series = "Proceedings - 20th Anniversary IEEE International SOC Conference",

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AB - A zero-overhead dynamic optically reconfigurable gate array (ZO-DORGA), based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory, has been proposed to realize both a high gate-count and zero-overhead rapid reconfiguration. This paper presents the world's largest 11,424 gate-count zero-overhead VLSI chip fabricated on a 96.04 mm2 chip using 0.35 μm-3 metal CMOS process technology. The optical reconfiguration circuit, the gate array structure, the CAD layout, and the performance of ZO-DORGA-VLSI are described, with reference to experimental results related to the reconfiguration period and retention time.

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An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

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