TY - GEN
T1 - An 11,424-gate dynamic optically reconfigurable gate array VLSI
AU - Nakajima, Mao
AU - Watanabe, Minoru
PY - 2008
Y1 - 2008
N2 - A DORGA architecture has been proposed to increase gate density. It uses the junction capacitance of photo-diodes as dynamic memory, thereby obviating the static configuration memory. This paper presents the world's largest 11,424 gate-count dynamic optically reconfigurable gate array (DORGA) VLSI fabricated on a 96.04 mm2 chip using a 0.35 μm three-metal CMOS process technology and a perfect optical system using a holographic memory. The advantages of this architecture are discussed in relation to the results described herein.
AB - A DORGA architecture has been proposed to increase gate density. It uses the junction capacitance of photo-diodes as dynamic memory, thereby obviating the static configuration memory. This paper presents the world's largest 11,424 gate-count dynamic optically reconfigurable gate array (DORGA) VLSI fabricated on a 96.04 mm2 chip using a 0.35 μm three-metal CMOS process technology and a perfect optical system using a holographic memory. The advantages of this architecture are discussed in relation to the results described herein.
UR - http://www.scopus.com/inward/record.url?scp=63049130977&partnerID=8YFLogxK
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U2 - 10.1109/FPT.2008.4762401
DO - 10.1109/FPT.2008.4762401
M3 - Conference contribution
AN - SCOPUS:63049130977
SN - 9781424427963
T3 - Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008
SP - 293
EP - 296
BT - Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008
T2 - 2008 International Conference on Field-Programmable Technology, ICFPT 2008
Y2 - 7 December 2008 through 10 December 2008
ER -