Abstract
This paper proposes a method for implementing a metric computation accelerator for fractal image compression using reconfigurable hardware. The most time-consuming part in the encoding of this compression is computation of metrics among image blocks. In our method, each processing element (PE) configured for an image block accelerates these computations by pipeline processing. Furthermore, by configuring the PE for a specific image block, we can reduce the number of adders, which are the main computing elements, by a half even in the worst case.
| Original language | English |
|---|---|
| Pages (from-to) | 372-377 |
| Number of pages | 6 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E84-A |
| Issue number | 1 |
| Publication status | Published - Jan 2001 |
| Externally published | Yes |
Keywords
- Fractal image compression
- Metric computation
- Pipeline processing
- Reconfigurable hardware
ASJC Scopus subject areas
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics