Analysis of retention time under multi-configuration on a DORGA

Daisaku Seto, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Optically reconfigurable gate arrays (ORGAs) have been developed to realize a large virtual gate count by adding a holographic memory onto a programmable gate array VLSI. Up to now, dynamic optically reconfigurable architecture has been proposed to increase the gate count of the ORGA-VLSI part, which uses photodiodes as dynamic memory to store a configuration context and perfectly removes static configuration memories. Consequently, extremely high gate count ORGAs have been realized. However, in this architecture, since background diffraction light of configuration contexts reduces the retention time of circuit information stored in junction capacitances of photodiodes, it has remained a concern that under multiconfiguration, an optical configuration can reduce the retention time of other circuits that have already been programmed before the configuration and are functioning on a gate array. This paper clarifies that the dynamic optically reconfigurable architecture is effective even under multi-configuration.

Original languageEnglish
Title of host publication2008 IEEE International SOC Conference, SOCC
Number of pages4
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE International SOC Conference, SOCC - Newport Beach, CA, United States
Duration: Sept 17 2008Sept 20 2008

Publication series

Name2008 IEEE International SOC Conference, SOCC


Conference2008 IEEE International SOC Conference, SOCC
Country/TerritoryUnited States
CityNewport Beach, CA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering


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