Analytical investigation on design instruction to avoid oscillatory false triggering of fast switching SiC-MOSFETs

SiC-MOSFETs have attracting increasing attention because of their outstanding characteristics that contributes to high efficiency and high power density of power converters. However, compared to conventional Si-IGBTs, SiC-MOSFETs are susceptible to false triggering, because they tend to generate large switching noise due to ultrafast switching capability and have a lower threshold voltage in high temperature operation. Particularly, disastrous oscillation of repetitive false triggering can occur after a fast turn-off, which is the severe issue for practical application of SiC-MOSFETs. The purpose of this paper is to give an instruction to avoid this phenomenon. This paper hypothesized that the repetitive false triggering is the parasitic oscillation caused by parasitic capacitance of SiC-MOSFET, and parasitic inductance of wiring. Based on this hypothesis, this paper analyzed the oscillatory condition of the parasitic oscillator to propose a design instruction to avoid the oscillatory false triggering. The result revealed that the parasitic inductance of the gate, drain, and source wiring should be designed so that the resonance frequency of the parasitic LC resonator in the gating circuit is far apart from that of the power circuit. This paper also presents experimental results that support appropriateness of the proposed design instruction.