TY - GEN
T1 - Asynchronous PipeRench
T2 - 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003
AU - Kagotani, H.
AU - Schmit, H.
PY - 2003/1/1
Y1 - 2003/1/1
N2 - PipeRench is a configurable architecture that has the unique ability to virtualize an application using dynamic reconfiguration. This paper investigates the potential benefits and costs of implementing this architecture using an asynchronous methodology. Since clock distribution and gating are relatively easy in the synchronous PipeRench, we focus on the benefit due to decreased timing pessimism in an asynchronous implementation. Two architectures for fully asynchronous implementation are considered. PE-based asynchronous implementation yields approximately 80% improvement in performance per stripe. This implementation, however, requires significant increases in configuration storage and wire count. A few particular features of the architecture, such as the crossbar interconnect structure within the stripe, are primarily responsible for this growth in configuration bits and wires. These features, however, are the primary aspects of the PipeRench architecture that make it a good compilation target.
AB - PipeRench is a configurable architecture that has the unique ability to virtualize an application using dynamic reconfiguration. This paper investigates the potential benefits and costs of implementing this architecture using an asynchronous methodology. Since clock distribution and gating are relatively easy in the synchronous PipeRench, we focus on the benefit due to decreased timing pessimism in an asynchronous implementation. Two architectures for fully asynchronous implementation are considered. PE-based asynchronous implementation yields approximately 80% improvement in performance per stripe. This implementation, however, requires significant increases in configuration storage and wire count. A few particular features of the architecture, such as the crossbar interconnect structure within the stripe, are primarily responsible for this growth in configuration bits and wires. These features, however, are the primary aspects of the PipeRench architecture that make it a good compilation target.
KW - Clocks
KW - Computer architecture
KW - Fabrics
KW - Field programmable gate arrays
KW - Logic
KW - Microprocessors
KW - Power dissipation
KW - Registers
KW - Timing
KW - Wires
UR - http://www.scopus.com/inward/record.url?scp=77950432456&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77950432456&partnerID=8YFLogxK
U2 - 10.1109/FPGA.2003.1227248
DO - 10.1109/FPGA.2003.1227248
M3 - Conference contribution
AN - SCOPUS:77950432456
T3 - IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings
SP - 121
EP - 129
BT - Proceedings - 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2003
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 April 2003 through 11 April 2003
ER -