TY - GEN
T1 - Configuration on an optically reconfigurable gate array under the maximum 120°C temperature condition
AU - Moriwaki, Retsu
AU - Watanabe, Minoru
AU - Ogiwara, Akifumi
N1 - Funding Information:
The VLSI chip used for this study was made with assistance of Rohm Co. Ltd. and Toppan Printing Co. Ltd. in the VLSI Design and Education Center (VDEC) chip fabrication program, The University of Tokyo.
Publisher Copyright:
Copyright © 2013 IEICE.
PY - 2013
Y1 - 2013
N2 - This paper presents a new wide-temperature condition acceptable optically reconfigurable gate array that can function well at 10-120°C temperature conditions. That and other features make this device very suitable for space applications.
AB - This paper presents a new wide-temperature condition acceptable optically reconfigurable gate array that can function well at 10-120°C temperature conditions. That and other features make this device very suitable for space applications.
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M3 - Conference contribution
AN - SCOPUS:85136830479
T3 - Optics InfoBase Conference Papers
BT - OptoElectronics and Communications Conference and Photonics in Switching, OECC 2013
PB - Optica Publishing Group (formerly OSA)
T2 - OptoElectronics and Communications Conference and Photonics in Switching, OECC 2013
Y2 - 30 June 2013 through 4 July 2013
ER -