Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

Daisaku Seto; Mao Nakajima; Minoru Watanabe

doi:10.1364/AO.49.006986

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

Daisaku Seto, Mao Nakajima, Minoru Watanabe

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96:04 mm² chip using an 0:35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2:21 μs partial reconfiguration.

Original language	English
Pages (from-to)	6986-6994
Number of pages	9
Journal	Applied Optics
Volume	49
Issue number	36
DOIs	https://doi.org/10.1364/AO.49.006986
Publication status	Published - Dec 20 2010
Externally published	Yes

ASJC Scopus subject areas

Atomic and Molecular Physics, and Optics
Engineering (miscellaneous)
Electrical and Electronic Engineering

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10.1364/AO.49.006986

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title = "Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability",

abstract = "We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96:04 mm2 chip using an 0:35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2:21 μs partial reconfiguration.",

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N2 - We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96:04 mm2 chip using an 0:35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2:21 μs partial reconfiguration.

AB - We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96:04 mm2 chip using an 0:35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2:21 μs partial reconfiguration.

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Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

Abstract

ASJC Scopus subject areas

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