Abstract
Design points and the results seen in the development of a dynamically reconfigurable logic LSI, PCA-2, are described. PCA-2 enables the realization of flexible parallel processing based on the autonomous reconfiguration of logic circuits. To realize this feature, we introduce an asynchronous circuit design and a homogeneous cell array structure. PCA-2 represents an advance on the earlier LSI, PCA-1. Cutting edge CMOS technology is used to realize the structural merits of PCA hardware. Compared to PCA-1, PCA-2 offers 16 times greater integration level for programmable logic. Due to miniaturization and design refinement, PCA-2 provides a 6-fold increase in the circuit frequency of the configuration controller and a 3-fold increase in the operating frequency of the programmable logic. The results gained confirm the effects of refinement and the suitability of our architecture for device miniaturization.
Original language | English |
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Pages (from-to) | 2011-2020 |
Number of pages | 10 |
Journal | IEICE Transactions on Information and Systems |
Volume | E87-D |
Issue number | 8 |
Publication status | Published - Aug 2004 |
Externally published | Yes |
Keywords
- Asynchronous circuit
- Autonomous reconfiguration
- Dynamically reconfigurable hardware
- Parallel computing
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Vision and Pattern Recognition
- Electrical and Electronic Engineering
- Artificial Intelligence