TY - GEN
T1 - Dynamically reconfigurable vision-chip architecture
AU - Yasuda, Maki
AU - Watanabe, Minoru
PY - 2010
Y1 - 2010
N2 - Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analogtype vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper presents a proposal for a dynamically reconfigurable vision chip architecture. In addition, some experimental results are reported.
AB - Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analogtype vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper presents a proposal for a dynamically reconfigurable vision chip architecture. In addition, some experimental results are reported.
KW - Dynamically reconfigurable devices
KW - Field programmable gate arrays
KW - Vision chips
UR - http://www.scopus.com/inward/record.url?scp=79951750120&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79951750120&partnerID=8YFLogxK
U2 - 10.1109/FPL.2010.101
DO - 10.1109/FPL.2010.101
M3 - Conference contribution
AN - SCOPUS:79951750120
SN - 9780769541792
T3 - Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010
SP - 508
EP - 512
BT - Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010
T2 - 20th International Conference on Field Programmable Logic and Applications, FPL 2010
Y2 - 31 August 2010 through 2 September 2010
ER -