EMC macro-modeling of CMOS inverter using LECCS-I/O model with additional current source

Kengo Iokibe; Akihiro Ohsaki; Yoshitaka Toyota; Ryuji Koga; Osami Wada

doi:10.1109/ISEMC.2008.4652105

EMC macro-modeling of CMOS inverter using LECCS-I/O model with additional current source

Kengo Iokibe, Akihiro Ohsaki, Yoshitaka Toyota, Ryuji Koga, Osami Wada

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.

Original language	English
Article number	4652105
Journal	IEEE International Symposium on Electromagnetic Compatibility
Volume	2008-January
DOIs	https://doi.org/10.1109/ISEMC.2008.4652105
Publication status	Published - Jan 1 2008
Event	2008 IEEE International Symposium on Electromagnetic Compatibility, EMC 2008 - Detroit, MI, Germany Duration: Aug 18 2008 → Aug 22 2008

ASJC Scopus subject areas

Condensed Matter Physics
Electrical and Electronic Engineering

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10.1109/ISEMC.2008.4652105

Cite this

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title = "EMC macro-modeling of CMOS inverter using LECCS-I/O model with additional current source",

abstract = "The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.",

author = "Kengo Iokibe and Akihiro Ohsaki and Yoshitaka Toyota and Ryuji Koga and Osami Wada",

year = "2008",

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note = "2008 IEEE International Symposium on Electromagnetic Compatibility, EMC 2008 ; Conference date: 18-08-2008 Through 22-08-2008",

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T1 - EMC macro-modeling of CMOS inverter using LECCS-I/O model with additional current source

AU - Iokibe, Kengo

AU - Ohsaki, Akihiro

AU - Toyota, Yoshitaka

AU - Koga, Ryuji

AU - Wada, Osami

PY - 2008/1/1

Y1 - 2008/1/1

N2 - The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.

AB - The authors investigated an EMC macro-model of the CMOS logic inverter gate, named LECCS-I/O that consists of linear equivalent circuit and current sources. This paper modifies the macro-model by adding another current source to express the short-circuit current in the inverter. The macro-model was determined from SPICE calculations of impedance and power current by using a device model of an inverter IC. The modified model was tested with several load capacitances in SPICE simulation. The results showed that the macro-model predicts the power current with good accuracy in the range up to 3 GHz except for frequencies at which inductances of the package and of traces on printed circuit board and capacitance of the load caused resonances.

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JO - IEEE International Symposium on Electromagnetic Compatibility

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EMC macro-modeling of CMOS inverter using LECCS-I/O model with additional current source

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