TY - JOUR
T1 - Fast method for timing verification that uses the conditions that cause changes in the output values of gates
AU - Ohnishi, Atsushi
AU - Sugiyama, Yuji
N1 - Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.
PY - 2001/1
Y1 - 2001/1
N2 - This paper discusses a fast method for timing verification which uses the conditions that cause changes in the output value of gates in a combinational logic circuit. The methods proposed previously derive the conditions that make a circuit behave correctly and incorrectly, but the new method in this paper derives only the latter. The new method also efficiently decides whether the derived condition is satisfied or not.
AB - This paper discusses a fast method for timing verification which uses the conditions that cause changes in the output value of gates in a combinational logic circuit. The methods proposed previously derive the conditions that make a circuit behave correctly and incorrectly, but the new method in this paper derives only the latter. The new method also efficiently decides whether the derived condition is satisfied or not.
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U2 - 10.1002/1520-684X(200101)32:1<38::AID-SCJ5>3.0.CO;2-F
DO - 10.1002/1520-684X(200101)32:1<38::AID-SCJ5>3.0.CO;2-F
M3 - Article
AN - SCOPUS:0035156107
SN - 0882-1666
VL - 32
SP - 38
EP - 44
JO - Systems and Computers in Japan
JF - Systems and Computers in Japan
IS - 1
ER -