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Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs
Koki Abe, Masataka Ishihara, Yusuke Hatakenaka, Kazuhiro Umetani, Eiji Hiraki
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
1
Citation
(Scopus)