Gate density advantage of parallel-operation-oriented FPGA architecture

Takumi Fujimori, Minora Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Recently, many studies of field programmable gate array (FPGA) hardware accelerators have been reported, in addition to studies of general-purpose computing on graphics processing units (GPGPUs), Xeon Phi, and so on. Since parallel processing is indispensable for such accelerating applications on FPGAs, implementing numerous parallel processing circuits is important to improve the performance of such FPGA hardware accelerators. When implementing a parallel operation for a conventional FPGA, some waste occurs: the same context is stored on numerous regions of configuration memory. This waste presents a critical issue because FPGAs used as accelerators perform parallel processing exclusively in most cases. This paper therefore proposes a parallel-operation-oriented FPGA exploiting a common configuration context. Herein, we describe the advantages of gate density, propagation delay, and compilation time in parallel-operation-oriented FPGAs.

Original languageEnglish
Title of host publication2017 IEEE National Aerospace and Electronics Conference, NAECON 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781538632000
Publication statusPublished - Jul 2 2017
Externally publishedYes
Event2017 IEEE National Aerospace and Electronics Conference, NAECON 2017 - Dayton, United States
Duration: Jun 27 2017Jun 30 2017

Publication series

NameProceedings of the IEEE National Aerospace Electronics Conference, NAECON
ISSN (Print)0547-3578
ISSN (Electronic)2379-2027


Conference2017 IEEE National Aerospace and Electronics Conference, NAECON 2017
Country/TerritoryUnited States

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering


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