TY - GEN
T1 - Gate density advantage of parallel-operation-oriented FPGA architecture
AU - Fujimori, Takumi
AU - Watanabe, Minora
N1 - Funding Information:
This research was partly supported by the Ministry of Education, Science, Sports and Culture, Grant-in-Aid for JSPS Research Fellow, No. 16J12063 and Grant-in-Aid for Scientific Research(B), No. 15H02676. The VLSI chip in this study was fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Rohm Co. Ltd. and Toppan Printing Co. Ltd.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/2
Y1 - 2017/7/2
N2 - Recently, many studies of field programmable gate array (FPGA) hardware accelerators have been reported, in addition to studies of general-purpose computing on graphics processing units (GPGPUs), Xeon Phi, and so on. Since parallel processing is indispensable for such accelerating applications on FPGAs, implementing numerous parallel processing circuits is important to improve the performance of such FPGA hardware accelerators. When implementing a parallel operation for a conventional FPGA, some waste occurs: the same context is stored on numerous regions of configuration memory. This waste presents a critical issue because FPGAs used as accelerators perform parallel processing exclusively in most cases. This paper therefore proposes a parallel-operation-oriented FPGA exploiting a common configuration context. Herein, we describe the advantages of gate density, propagation delay, and compilation time in parallel-operation-oriented FPGAs.
AB - Recently, many studies of field programmable gate array (FPGA) hardware accelerators have been reported, in addition to studies of general-purpose computing on graphics processing units (GPGPUs), Xeon Phi, and so on. Since parallel processing is indispensable for such accelerating applications on FPGAs, implementing numerous parallel processing circuits is important to improve the performance of such FPGA hardware accelerators. When implementing a parallel operation for a conventional FPGA, some waste occurs: the same context is stored on numerous regions of configuration memory. This waste presents a critical issue because FPGAs used as accelerators perform parallel processing exclusively in most cases. This paper therefore proposes a parallel-operation-oriented FPGA exploiting a common configuration context. Herein, we describe the advantages of gate density, propagation delay, and compilation time in parallel-operation-oriented FPGAs.
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U2 - 10.1109/NAECON.2017.8268761
DO - 10.1109/NAECON.2017.8268761
M3 - Conference contribution
AN - SCOPUS:85045231729
T3 - Proceedings of the IEEE National Aerospace Electronics Conference, NAECON
SP - 155
EP - 158
BT - 2017 IEEE National Aerospace and Electronics Conference, NAECON 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE National Aerospace and Electronics Conference, NAECON 2017
Y2 - 27 June 2017 through 30 June 2017
ER -