Hardware/software codesign method for a general purpose reconfigurable co-processor

Shinji Kimura; Mitsuteru Yukishita; Yasufumi Itou; Akira Nagoya; Makoto Hirao; Katumasa Watanabe

Hardware/software codesign method for a general purpose reconfigurable co-processor

Shinji Kimura, Mitsuteru Yukishita, Yasufumi Itou, Akira Nagoya, Makoto Hirao, Katumasa Watanabe

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGA's, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via the DMA based memory sharing. We also show cooperation examples and the effectiveness of our approach for the fast execution of user processes.

Original language	English
Pages	147-151
Number of pages	5
Publication status	Published - Jan 1 1997
Externally published	Yes
Event	Proceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97 - Braunschweig, Ger Duration: Mar 24 1997 → Mar 26 1997

Other

Other	Proceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97
City	Braunschweig, Ger
Period	3/24/97 → 3/26/97

ASJC Scopus subject areas

Hardware and Architecture

Cite this

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title = "Hardware/software codesign method for a general purpose reconfigurable co-processor",

abstract = "This paper shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGA's, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via the DMA based memory sharing. We also show cooperation examples and the effectiveness of our approach for the fast execution of user processes.",

author = "Shinji Kimura and Mitsuteru Yukishita and Yasufumi Itou and Akira Nagoya and Makoto Hirao and Katumasa Watanabe",

year = "1997",

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language = "English",

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T1 - Hardware/software codesign method for a general purpose reconfigurable co-processor

AU - Kimura, Shinji

AU - Yukishita, Mitsuteru

AU - Itou, Yasufumi

AU - Nagoya, Akira

AU - Hirao, Makoto

AU - Watanabe, Katumasa

PY - 1997/1/1

Y1 - 1997/1/1

N2 - This paper shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGA's, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via the DMA based memory sharing. We also show cooperation examples and the effectiveness of our approach for the fast execution of user processes.

AB - This paper shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGA's, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via the DMA based memory sharing. We also show cooperation examples and the effectiveness of our approach for the fast execution of user processes.

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T2 - Proceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97

Y2 - 24 March 1997 through 26 March 1997

ER -

Hardware/software codesign method for a general purpose reconfigurable co-processor

Abstract

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ASJC Scopus subject areas

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