TY - GEN
T1 - Holographic memory calculation FPGA accelerator for optically reconfigurable gate arrays
AU - Fujimori, Takumi
AU - Watanabe, Minoru
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2018/3/29
Y1 - 2018/3/29
N2 - Recently, radiation-hardened optically reconfigurable gate arrays have been developed for space applications. An optically reconfigurable gate array comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. Since the optically reconfigurable gate array is a type of multi-context field programmable gate array (FPGA), several configuration contexts must be implemented onto the holographic memory on an optically reconfigurable gate array. However, the holographic memory pattern calculation is a heavy operation in addition to logic synthesis and to place and route operations. This paper therefore presents an FPGA hardware accelerator for hologram memory calculation for optically reconfigurable gate arrays with an FPGA (Cyclone V; Altera Corp.).Performance evaluation results show that the calculation speed of a hologram memory pattern including 512 bright bits is 16.9 times higher than multi-thread calculation on the CPU (Core i7-4770; Intel Corp.). Furthermore, the FPGA hardware accelerator power consumption is only 6 W, compared to 95 W of the CPU (Core i7-4770; Intel Corp.).
AB - Recently, radiation-hardened optically reconfigurable gate arrays have been developed for space applications. An optically reconfigurable gate array comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. Since the optically reconfigurable gate array is a type of multi-context field programmable gate array (FPGA), several configuration contexts must be implemented onto the holographic memory on an optically reconfigurable gate array. However, the holographic memory pattern calculation is a heavy operation in addition to logic synthesis and to place and route operations. This paper therefore presents an FPGA hardware accelerator for hologram memory calculation for optically reconfigurable gate arrays with an FPGA (Cyclone V; Altera Corp.).Performance evaluation results show that the calculation speed of a hologram memory pattern including 512 bright bits is 16.9 times higher than multi-thread calculation on the CPU (Core i7-4770; Intel Corp.). Furthermore, the FPGA hardware accelerator power consumption is only 6 W, compared to 95 W of the CPU (Core i7-4770; Intel Corp.).
KW - Field programmable gate array
KW - Optically reconfigurable gate array
UR - http://www.scopus.com/inward/record.url?scp=85048096107&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85048096107&partnerID=8YFLogxK
U2 - 10.1109/DASC-PICom-DataCom-CyberSciTec.2017.109
DO - 10.1109/DASC-PICom-DataCom-CyberSciTec.2017.109
M3 - Conference contribution
AN - SCOPUS:85048096107
T3 - Proceedings - 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017
SP - 620
EP - 625
BT - Proceedings - 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE International Conference on Dependable, Autonomic and Secure Computing, 2017 IEEE 15th International Conference on Pervasive Intelligence and Computing, 2017 IEEE 3rd International Conference on Big Data Intelligence and Computing and 2017 IEEE Cyber Science and Technology Congress, DASC-PICom-DataCom-CyberSciTec 2017
Y2 - 6 November 2017 through 11 November 2017
ER -