TY - GEN
T1 - Hybrid sample rate converter with 110dB SNR and 1/10 less logic gates
AU - Inoue, Manabu
AU - Kobayashi, Fuminori
AU - Watanabe, Minoru
PY - 2006
Y1 - 2006
N2 - An SRC, sampling rate converter, consisting of conventional filter-type SRC and time-domain SRC using Fourier interpolation algorithm is proposed. Filter portion realizes over-sampling, and its output is interpolated by the Fourier portion. The SRC achieves noise level of as low as -110dB for all frequencies, and its gate count is about 1000000 FPGA logic cells.
AB - An SRC, sampling rate converter, consisting of conventional filter-type SRC and time-domain SRC using Fourier interpolation algorithm is proposed. Filter portion realizes over-sampling, and its output is interpolated by the Fourier portion. The SRC achieves noise level of as low as -110dB for all frequencies, and its gate count is about 1000000 FPGA logic cells.
UR - http://www.scopus.com/inward/record.url?scp=34250830126&partnerID=8YFLogxK
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U2 - 10.1109/EIT.2006.252121
DO - 10.1109/EIT.2006.252121
M3 - Conference contribution
AN - SCOPUS:34250830126
SN - 078039593X
SN - 9780780395930
T3 - 2006 IEEE International Conference on Electro Information Technology
SP - 432
EP - 436
BT - 2006 IEEE International Conference on Electro Information Technology
T2 - 2006 IEEE International Conference on Electro Information Technology
Y2 - 7 May 2006 through 10 May 2006
ER -