Image recognition operation on a dynamically reconfigurable vison architecture

Yuki Kamikubo; Minoru Watanabe; Shoji Kawahito

doi:10.1109/FPL.2013.6645603

Image recognition operation on a dynamically reconfigurable vison architecture

Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito

Research output: Contribution to conference › Paper › peer-review

Abstract

Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.

Original language	English
DOIs	https://doi.org/10.1109/FPL.2013.6645603
Publication status	Published - 2013
Externally published	Yes
Event	2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Porto, Portugal Duration: Sept 2 2013 → Sept 4 2013

Conference

Conference	2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013
Country/Territory	Portugal
City	Porto
Period	9/2/13 → 9/4/13

Keywords

Dynamically re-configurable devices
Field Programmable Gate Arrays
Vision chips

ASJC Scopus subject areas

Computational Theory and Mathematics
Applied Mathematics

Access to Document

10.1109/FPL.2013.6645603

Cite this

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title = "Image recognition operation on a dynamically reconfigurable vison architecture",

abstract = "Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.",

keywords = "Dynamically re-configurable devices, Field Programmable Gate Arrays, Vision chips",

author = "Yuki Kamikubo and Minoru Watanabe and Shoji Kawahito",

year = "2013",

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language = "English",

note = "2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 ; Conference date: 02-09-2013 Through 04-09-2013",

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AU - Kamikubo, Yuki

AU - Watanabe, Minoru

AU - Kawahito, Shoji

PY - 2013

Y1 - 2013

N2 - Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.

AB - Recently, for use in autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. However, to recognize numerous images quickly, such systems require many template images to be read out dynamically from memory. They must then be sent to a processor quickly. Achieving such high-speed real-time image recognition operation is difficult because of the bottleneck of the transfer between the memory and the processor. To alleviate that bottleneck, a dynamically reconfigurable vision architecture was proposed. This paper presents 16-gray scale image recognition operation of the proposed architecture.

KW - Dynamically re-configurable devices

KW - Field Programmable Gate Arrays

KW - Vision chips

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T2 - 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013

Y2 - 2 September 2013 through 4 September 2013

ER -

Image recognition operation on a dynamically reconfigurable vison architecture

Abstract

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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