LUT-based FPGA technology mapping using permissible functions

Takayuki Suyama, Hiroshi Sawada, Akira Nagoya

Research output: Contribution to conferencePaperpeer-review


In this paper we present a method that maps a loop-free multilevel combinational circuit into Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using permissible functions. When mapping a minimized circuit into LUTs, a characteristic difference between an LUT and simple gates causes ineffective use of the LUT. Using permissible functions, the circuit is adroitly adapted for an LUT that has n inputs, one output, and can implement any n-variable Boolean function. We have implemented this method and carried out some experiments. Results show that this method is useful to refine initial mapping to LUTs.

Original languageEnglish
Number of pages4
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 9th International Conference on VLSI Design - Bangalore, India
Duration: Jan 3 1996Jan 6 1996


OtherProceedings of the 1996 9th International Conference on VLSI Design
CityBangalore, India

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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