LUT-based FPGA technology mapping using permissible functions

Takayuki Suyama; Hiroshi Sawada; Akira Nagoya

LUT-based FPGA technology mapping using permissible functions

Takayuki Suyama, Hiroshi Sawada, Akira Nagoya

Research output: Contribution to conference › Paper › peer-review

Abstract

In this paper we present a method that maps a loop-free multilevel combinational circuit into Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using permissible functions. When mapping a minimized circuit into LUTs, a characteristic difference between an LUT and simple gates causes ineffective use of the LUT. Using permissible functions, the circuit is adroitly adapted for an LUT that has n inputs, one output, and can implement any n-variable Boolean function. We have implemented this method and carried out some experiments. Results show that this method is useful to refine initial mapping to LUTs.

Original language	English
Pages	215-218
Number of pages	4
Publication status	Published - 1996
Externally published	Yes
Event	Proceedings of the 1996 9th International Conference on VLSI Design - Bangalore, India Duration: Jan 3 1996 → Jan 6 1996

Other

Other	Proceedings of the 1996 9th International Conference on VLSI Design
City	Bangalore, India
Period	1/3/96 → 1/6/96

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

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title = "LUT-based FPGA technology mapping using permissible functions",

abstract = "In this paper we present a method that maps a loop-free multilevel combinational circuit into Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using permissible functions. When mapping a minimized circuit into LUTs, a characteristic difference between an LUT and simple gates causes ineffective use of the LUT. Using permissible functions, the circuit is adroitly adapted for an LUT that has n inputs, one output, and can implement any n-variable Boolean function. We have implemented this method and carried out some experiments. Results show that this method is useful to refine initial mapping to LUTs.",

author = "Takayuki Suyama and Hiroshi Sawada and Akira Nagoya",

note = "Copyright: Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.; Proceedings of the 1996 9th International Conference on VLSI Design ; Conference date: 03-01-1996 Through 06-01-1996",

year = "1996",

language = "English",

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AU - Suyama, Takayuki

AU - Sawada, Hiroshi

AU - Nagoya, Akira

PY - 1996

Y1 - 1996

N2 - In this paper we present a method that maps a loop-free multilevel combinational circuit into Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using permissible functions. When mapping a minimized circuit into LUTs, a characteristic difference between an LUT and simple gates causes ineffective use of the LUT. Using permissible functions, the circuit is adroitly adapted for an LUT that has n inputs, one output, and can implement any n-variable Boolean function. We have implemented this method and carried out some experiments. Results show that this method is useful to refine initial mapping to LUTs.

AB - In this paper we present a method that maps a loop-free multilevel combinational circuit into Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) using permissible functions. When mapping a minimized circuit into LUTs, a characteristic difference between an LUT and simple gates causes ineffective use of the LUT. Using permissible functions, the circuit is adroitly adapted for an LUT that has n inputs, one output, and can implement any n-variable Boolean function. We have implemented this method and carried out some experiments. Results show that this method is useful to refine initial mapping to LUTs.

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T2 - Proceedings of the 1996 9th International Conference on VLSI Design

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ER -

LUT-based FPGA technology mapping using permissible functions

Abstract

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ASJC Scopus subject areas

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