MISC: Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -

Fuminori Kobayashi; Yasuyuki Morikawa; Minoru Watanabe

MISC: Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -

Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Though dynamic reconfiguration has been applied to processors to enhance performance, their simpleness cannot exceed some limitations. To solve this problem, this paper introduces a consideration based on the 6502 microprocessor, and find that the key to hardware reduction is microscopic partitioning of processor functions. In addition, the implementation depends on an integrated circuit with very fast optical reconfigurability. Its effectiveness, reduction in hardware amount down to one third, is demonstrated by a sample implementation of 6502 on a Xilinx Virtex-II Pro field-programmable gate array.

Original language	English
Title of host publication	Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
Pages	222-228
Number of pages	7
Publication status	Published - 2008
Externally published	Yes
Event	2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 - Las Vegas, NV, United States Duration: Jul 14 2008 → Jul 17 2008

Publication series

Name	Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

Conference

Conference	2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
Country/Territory	United States
City	Las Vegas, NV
Period	7/14/08 → 7/17/08

Keywords

ORGA
Partial configuration
Vertex-II Pro

ASJC Scopus subject areas

Computer Science Applications
Hardware and Architecture
Software

Cite this

Kobayashi, F., Morikawa, Y., & Watanabe, M. (2008). MISC: Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -. In Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 (pp. 222-228). (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

MISC: Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -. / Kobayashi, Fuminori; Morikawa, Yasuyuki; Watanabe, Minoru.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. 2008. p. 222-228 (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kobayashi, F, Morikawa, Y & Watanabe, M 2008, MISC: Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -. in Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008, pp. 222-228, 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008, Las Vegas, NV, United States, 7/14/08.

Kobayashi F, Morikawa Y, Watanabe M. MISC: Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -. In Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. 2008. p. 222-228. (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

Kobayashi, Fuminori ; Morikawa, Yasuyuki ; Watanabe, Minoru. / MISC : Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -. Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008. 2008. pp. 222-228 (Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008).

@inproceedings{e5f0b8b6b80645389a925f1ab81fb2d6,

title = "MISC: Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -",

abstract = "Though dynamic reconfiguration has been applied to processors to enhance performance, their simpleness cannot exceed some limitations. To solve this problem, this paper introduces a consideration based on the 6502 microprocessor, and find that the key to hardware reduction is microscopic partitioning of processor functions. In addition, the implementation depends on an integrated circuit with very fast optical reconfigurability. Its effectiveness, reduction in hardware amount down to one third, is demonstrated by a sample implementation of 6502 on a Xilinx Virtex-II Pro field-programmable gate array.",

keywords = "ORGA, Partial configuration, Vertex-II Pro",

author = "Fuminori Kobayashi and Yasuyuki Morikawa and Minoru Watanabe",

year = "2008",

language = "English",

isbn = "1601320647",

series = "Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008",

pages = "222--228",

booktitle = "Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008",

note = "2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 ; Conference date: 14-07-2008 Through 17-07-2008",

}

TY - GEN

T1 - MISC

T2 - 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

AU - Kobayashi, Fuminori

AU - Morikawa, Yasuyuki

AU - Watanabe, Minoru

PY - 2008

Y1 - 2008

N2 - Though dynamic reconfiguration has been applied to processors to enhance performance, their simpleness cannot exceed some limitations. To solve this problem, this paper introduces a consideration based on the 6502 microprocessor, and find that the key to hardware reduction is microscopic partitioning of processor functions. In addition, the implementation depends on an integrated circuit with very fast optical reconfigurability. Its effectiveness, reduction in hardware amount down to one third, is demonstrated by a sample implementation of 6502 on a Xilinx Virtex-II Pro field-programmable gate array.

AB - Though dynamic reconfiguration has been applied to processors to enhance performance, their simpleness cannot exceed some limitations. To solve this problem, this paper introduces a consideration based on the 6502 microprocessor, and find that the key to hardware reduction is microscopic partitioning of processor functions. In addition, the implementation depends on an integrated circuit with very fast optical reconfigurability. Its effectiveness, reduction in hardware amount down to one third, is demonstrated by a sample implementation of 6502 on a Xilinx Virtex-II Pro field-programmable gate array.

KW - ORGA

KW - Partial configuration

KW - Vertex-II Pro

UR - http://www.scopus.com/inward/record.url?scp=62649093510&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62649093510&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:62649093510

SN - 1601320647

SN - 9781601320643

T3 - Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

SP - 222

EP - 228

BT - Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008

Y2 - 14 July 2008 through 17 July 2008

ER -

MISC: Mono instruction-set computer based on dynamic reconfiguration - A 6502 perspective -

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

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