TY - GEN
T1 - Othello solver based on a soft-core MIMD processor array
AU - Mabuchi, Takayuki
AU - Watanabe, Takahiro
AU - Moriwaki, Retsu
AU - Aoyama, Yuji
AU - Gundjalam, Amarjargal
AU - Yamaji, Yuichiro
AU - Nakada, Hironari
AU - Watanabe, Minoru
PY - 2010
Y1 - 2010
N2 - This report presents an Othello Solver based on a 32-bit original soft-core Multiple Instruction stream, Multiple Data stream (MIMD) processor array targeting a single field programmable gate array (FPGA), Cyclone II (EP2C70D896C6N), on a DE2 Development and Education Board (Altera Corp.). The solver can execute a move-checking operation, a disc flipping operation, a move selection operation, an evaluation operation, and an alpha-beta pruning operation. The solver system includes a universal asynchronous receiver transmitter (UART) inside the FPGA and uses a RS-232C driver on the board so that the solver system can communicate with a personal computer or another FPGA according to the 2010 International Conference on Field Programmable Technology (FPT) competition specifications. The solver can win all skill levels of a target software provided from the FPT conference within the time limit of 1/40 s. This report presents estimates the solver's performance based on the implementation results.
AB - This report presents an Othello Solver based on a 32-bit original soft-core Multiple Instruction stream, Multiple Data stream (MIMD) processor array targeting a single field programmable gate array (FPGA), Cyclone II (EP2C70D896C6N), on a DE2 Development and Education Board (Altera Corp.). The solver can execute a move-checking operation, a disc flipping operation, a move selection operation, an evaluation operation, and an alpha-beta pruning operation. The solver system includes a universal asynchronous receiver transmitter (UART) inside the FPGA and uses a RS-232C driver on the board so that the solver system can communicate with a personal computer or another FPGA according to the 2010 International Conference on Field Programmable Technology (FPT) competition specifications. The solver can win all skill levels of a target software provided from the FPT conference within the time limit of 1/40 s. This report presents estimates the solver's performance based on the implementation results.
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U2 - 10.1109/FPT.2010.5681470
DO - 10.1109/FPT.2010.5681470
M3 - Conference contribution
AN - SCOPUS:79551534080
SN - 9781424489817
T3 - Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
SP - 511
EP - 514
BT - Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
T2 - 2010 International Conference on Field-Programmable Technology, FPT'10
Y2 - 8 December 2010 through 10 December 2010
ER -