Over-sampling PLL for low-jitter and responsive clock synchronization

Manabu Inoue, Fuminori Kobayashi, Minoru Watanabe

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)


Phase Locked Loops (PLLs) are widely used in communication and required to provide low-jitter and fast frequency/phase locking capabilities. For improving these capabilities of PLL, an over-sampling phase detector (PD) using phase interpolation based on a counter with a high-frequency internal clock is proposed. PLL using normal PD compares phases of reference or input signal with its output at the time of their positive transition, but this PLL using over-sampling PD can compare phases more than once a cycle of reference. Thus, the PLL features less jitter than PLL using normal PD, and improved responsiveness. Also we optimized implementation of phase interpolation, to improve maximum operating frequency and circuit size. Experimental results including two jitter characteristics, vital in communication, are shown.

Original languageEnglish
Number of pages4
Publication statusPublished - 2006
Externally publishedYes
Event2006 International Symposium on Communications and Information Technologies, ISCIT - Bangkok, Thailand
Duration: Oct 18 2006Oct 20 2006


Conference2006 International Symposium on Communications and Information Technologies, ISCIT

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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