TY - GEN
T1 - Parallel template matching operations on a dynamically reconfigurable vision-chip architecture
AU - Nakada, Hironari
AU - Watanabe, Minora
AU - Kawahito, Shoji
PY - 2011
Y1 - 2011
N2 - Recently, high-speed image recognition functionality that is superior to the image recognition speed of the human eye is demanded for autonomous vehicles and robots. Currently, such embedded systems comprise a processor and memory. To recognize many images, many template images must be stored in memory and must be sent quickly from memory to the processor. For example, assuming that the system receives an external image with 1 million pixels at every 1 ms and assuming that the system must execute template-matching operations of 1 million template images with the same million pixels within 1 ms, then the transfer speed from the memory to the processor and the processor operation reaches 1 Petapixel/s. Therefore, to realize high-speed template-matching operation, a dynamically reconfigurable vision-chip architecture with a holographic memory and large-bandwidth optical connections has been proposed. Among such researches, this paper presents a proposal of novel parallel template-matching operations performed on the dynamically reconfigurable vision-chip architecture. Furthermore, the advantages of the new method are discussed based on some demonstration results.
AB - Recently, high-speed image recognition functionality that is superior to the image recognition speed of the human eye is demanded for autonomous vehicles and robots. Currently, such embedded systems comprise a processor and memory. To recognize many images, many template images must be stored in memory and must be sent quickly from memory to the processor. For example, assuming that the system receives an external image with 1 million pixels at every 1 ms and assuming that the system must execute template-matching operations of 1 million template images with the same million pixels within 1 ms, then the transfer speed from the memory to the processor and the processor operation reaches 1 Petapixel/s. Therefore, to realize high-speed template-matching operation, a dynamically reconfigurable vision-chip architecture with a holographic memory and large-bandwidth optical connections has been proposed. Among such researches, this paper presents a proposal of novel parallel template-matching operations performed on the dynamically reconfigurable vision-chip architecture. Furthermore, the advantages of the new method are discussed based on some demonstration results.
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U2 - 10.1109/NEWCAS.2011.5981291
DO - 10.1109/NEWCAS.2011.5981291
M3 - Conference contribution
AN - SCOPUS:80052526922
SN - 9781612841359
T3 - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
SP - 205
EP - 208
BT - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
T2 - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
Y2 - 26 June 2011 through 29 June 2011
ER -