Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture

Daisaku Seto; Minoru Watanabe

doi:10.1109/FPT.2007.4439262

Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, estimation ofa perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. This paper presents a perfect DORGA architecture including a holographic memory. The performances of the DORGA architecture, in particular the reconfiguration context retention time, were analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.

Original language	English
Title of host publication	ICFPT 2007 - International Conference on Field Programmable Technology
Pages	265-268
Number of pages	4
DOIs	https://doi.org/10.1109/FPT.2007.4439262
Publication status	Published - 2007
Externally published	Yes
Event	International Conference on Field Programmable Technology, ICFPT 2007 - Kitakyushu, Japan Duration: Dec 12 2007 → Dec 14 2007

Publication series

Name	ICFPT 2007 - International Conference on Field Programmable Technology

Conference

Conference	International Conference on Field Programmable Technology, ICFPT 2007
Country/Territory	Japan
City	Kitakyushu
Period	12/12/07 → 12/14/07

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/FPT.2007.4439262

Cite this

Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture. / Seto, Daisaku; Watanabe, Minoru.
ICFPT 2007 - International Conference on Field Programmable Technology. 2007. p. 265-268 4439262 (ICFPT 2007 - International Conference on Field Programmable Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Seto, D & Watanabe, M 2007, Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture. in ICFPT 2007 - International Conference on Field Programmable Technology., 4439262, ICFPT 2007 - International Conference on Field Programmable Technology, pp. 265-268, International Conference on Field Programmable Technology, ICFPT 2007, Kitakyushu, Japan, 12/12/07. https://doi.org/10.1109/FPT.2007.4439262

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doi = "10.1109/FPT.2007.4439262",

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AB - To increase gate density, a dynamic optically reconfigurable gate array (DORGA) architecture has been proposed that uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, estimation ofa perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. This paper presents a perfect DORGA architecture including a holographic memory. The performances of the DORGA architecture, in particular the reconfiguration context retention time, were analyzed experimentally. The advantages of this architecture are discussed in relation to the results of this study.

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Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture

Abstract

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Conference

ASJC Scopus subject areas

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