TY - GEN
T1 - Recovery method for a laser array failure on dynamic optically reconfigurable gate arrays
AU - Seto, Daisaku
AU - Watanabe, Minoru
PY - 2010
Y1 - 2010
N2 - Demand is increasing daily for a large-gate-count robust VLSI chip that can be used in a radiation-rich space environment. Since they exploit the large storage capacity of a holographic memory, optically reconfigurable gate arrays (ORGAs) have been developed to realize a much larger virtual gate count than those of current VLSI chips. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. Among such developments, dynamic optically reconfigurable gate arrays (DORGAs) have been developed to realize a high-gate-density VLSI using a photodiode memory architecture. Unfortunately, the DORGA architecture is more sensitive to the unallowable turn-off failure mode of a laser array. Therefore, this paper presents a recovery method for a turn-off failure mode of a laser array on a DORGA and its demonstration results.
AB - Demand is increasing daily for a large-gate-count robust VLSI chip that can be used in a radiation-rich space environment. Since they exploit the large storage capacity of a holographic memory, optically reconfigurable gate arrays (ORGAs) have been developed to realize a much larger virtual gate count than those of current VLSI chips. The ORGA architecture is extremely robust for many failure modes caused by high-energy charged particles. Among such developments, dynamic optically reconfigurable gate arrays (DORGAs) have been developed to realize a high-gate-density VLSI using a photodiode memory architecture. Unfortunately, the DORGA architecture is more sensitive to the unallowable turn-off failure mode of a laser array. Therefore, this paper presents a recovery method for a turn-off failure mode of a laser array on a DORGA and its demonstration results.
KW - Defect tolerance
KW - Field programmable gate arrays
KW - Laser arrays
KW - Optically reconfigurable gate arrays
UR - http://www.scopus.com/inward/record.url?scp=79952021722&partnerID=8YFLogxK
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U2 - 10.1109/DFT.2010.55
DO - 10.1109/DFT.2010.55
M3 - Conference contribution
AN - SCOPUS:79952021722
SN - 9780769542430
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SP - 411
EP - 419
BT - Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
T2 - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
Y2 - 6 October 2010 through 8 October 2010
ER -