Scaling rule of optically differential reconfigurable gate array VLSIs

Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically merely by increasing the reconfiguration frequency. Therefore, the reconfiguration time and reconfiguration overhead of next-generation programmable devices are extremely important parameters. To realize zero-overhead and short reconfiguration, an Optically Differential Reconfigurable Gate Array (ODRGA) VLSIs were developed. However, up to now, the scaling rule of ODRGAs has never been clarified. This paper describes the designs of ODRGA-VLSIs using 0.18 μm and 0.35 μm CMOS processes and presents discussion of the scaling rule of ODRGAs using layout results.

Original languageEnglish
Title of host publication2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
Pages128-131
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference - Montreal, QC, Canada
Duration: Aug 5 2007Aug 8 2007

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
Country/TerritoryCanada
CityMontreal, QC
Period8/5/078/8/07

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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