TY - GEN
T1 - Scaling rule of optically differential reconfigurable gate array VLSIs
AU - Watanabe, Minoru
AU - Shiki, Takenori
AU - Kobayashi, Fuminori
PY - 2007
Y1 - 2007
N2 - Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically merely by increasing the reconfiguration frequency. Therefore, the reconfiguration time and reconfiguration overhead of next-generation programmable devices are extremely important parameters. To realize zero-overhead and short reconfiguration, an Optically Differential Reconfigurable Gate Array (ODRGA) VLSIs were developed. However, up to now, the scaling rule of ODRGAs has never been clarified. This paper describes the designs of ODRGA-VLSIs using 0.18 μm and 0.35 μm CMOS processes and presents discussion of the scaling rule of ODRGAs using layout results.
AB - Dynamic reconfigurable devices present new computational paradigms because programmable devices' activity and performance can be improved dramatically merely by increasing the reconfiguration frequency. Therefore, the reconfiguration time and reconfiguration overhead of next-generation programmable devices are extremely important parameters. To realize zero-overhead and short reconfiguration, an Optically Differential Reconfigurable Gate Array (ODRGA) VLSIs were developed. However, up to now, the scaling rule of ODRGAs has never been clarified. This paper describes the designs of ODRGA-VLSIs using 0.18 μm and 0.35 μm CMOS processes and presents discussion of the scaling rule of ODRGAs using layout results.
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U2 - 10.1109/MWSCAS.2007.4488553
DO - 10.1109/MWSCAS.2007.4488553
M3 - Conference contribution
AN - SCOPUS:51449087371
SN - 1424411769
SN - 9781424411764
T3 - Midwest Symposium on Circuits and Systems
SP - 128
EP - 131
BT - 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
T2 - 2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
Y2 - 5 August 2007 through 8 August 2007
ER -