SOI pixel developments in a 0.15μm technology

While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and low-power applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15mm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI process. We hosted the second MPW run and invited foreign universities and laboratories to join this MPW run in addition to Japanese universities and laboratories. Features of these SOI devices and experiences with SOI pixel development are presented.