Synthesis of two‐phase quasi‐delay‐insensitive circuits from dependency graphs

Hiroto Kagotani, Takashi Nanya

Research output: Contribution to journalArticlepeer-review


Recently, the efficiency of asynchronous circuits has again attracted a great deal of attention. In this paper, a synthesis method of delay‐sensitive circuits is presented. In this method, a directed graph representing dependencies between microoperations such as register transfers and arithmetic operations is given as the specification of a circuit. Under some constraints of the graph for correct synthesis, the control circuit is implemented by translating graph nodes to the associated circuit blocks. It controls data‐paths in a two‐phase manner by handshakes. This method allows designers to describe parallelism easily in their specifications. The cost of synthesis is low.

Original languageEnglish
Pages (from-to)11-19
Number of pages9
JournalSystems and Computers in Japan
Issue number4
Publication statusPublished - 1995
Externally publishedYes


  • Asynchronous circuits
  • Circuit synthesis
  • Dependency graph
  • Quasi‐delay‐insensitive circuits

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics


Dive into the research topics of 'Synthesis of two‐phase quasi‐delay‐insensitive circuits from dependency graphs'. Together they form a unique fingerprint.

Cite this