Synthesis of two‐phase quasi‐delay‐insensitive circuits from dependency graphs

Recently, the efficiency of asynchronous circuits has again attracted a great deal of attention. In this paper, a synthesis method of delay‐sensitive circuits is presented. In this method, a directed graph representing dependencies between microoperations such as register transfers and arithmetic operations is given as the specification of a circuit. Under some constraints of the graph for correct synthesis, the control circuit is implemented by translating graph nodes to the associated circuit blocks. It controls data‐paths in a two‐phase manner by handshakes. This method allows designers to describe parallelism easily in their specifications. The cost of synthesis is low.