TY - GEN
T1 - Template matching operations on a dynamically reconfigurable vision-chip architecture
AU - Nakada, Hironari
AU - Watanabe, Minoru
PY - 2010
Y1 - 2010
N2 - Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper experimentally presents a template matching operations on a dynamically reconfigurable vision-chip architecture.
AB - Recently, for autonomous vehicles and robots, demand has been increasing for high-speed image recognition that is superior to that of the human eye. To date, analog-type vision chips and digital vision chips have been developed. Nevertheless, even now, to realize such high-speed real-time image recognition operation is extremely difficult. Therefore, to realize a high-speed real-time image-recognizable vision chip, this paper experimentally presents a template matching operations on a dynamically reconfigurable vision-chip architecture.
KW - Dynamically reconfigurable devices
KW - Field programmable gate arrays
KW - Vision chips
UR - http://www.scopus.com/inward/record.url?scp=78651235803&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78651235803&partnerID=8YFLogxK
U2 - 10.1109/ISCIT.2010.5665152
DO - 10.1109/ISCIT.2010.5665152
M3 - Conference contribution
AN - SCOPUS:78651235803
SN - 9781424470105
T3 - ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
SP - 1091
EP - 1096
BT - ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies
T2 - 2010 10th International Symposium on Communications and Information Technologies, ISCIT 2010
Y2 - 26 October 2010 through 29 October 2010
ER -