Test methodology for interconnect structures of LUT-based FPGAs

Hiroyuki Michinishi; Tokumi Yokohira; Takuji Okamoto; Tomoo Inoue; Hideo Fujiwara

Test methodology for interconnect structures of LUT-based FPGAs

Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validnesses and complexities.

Original language	English
Pages (from-to)	68-74
Number of pages	7
Journal	Proceedings of the Asian Test Symposium
Publication status	Published - 1996
Event	Proceedings of the 1996 5th Asian Test Symposium, ATS'96 - Hsinchu, Taiwan Duration: Nov 20 1996 → Nov 22 1996

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Test methodology for interconnect structures of LUT-based FPGAs",

abstract = "In this paper, we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validnesses and complexities.",

author = "Hiroyuki Michinishi and Tokumi Yokohira and Takuji Okamoto and Tomoo Inoue and Hideo Fujiwara",

year = "1996",

language = "English",

pages = "68--74",

journal = "Proceedings of the Asian Test Symposium",

issn = "1081-7735",

publisher = "IEEE Computer Society",

note = "Proceedings of the 1996 5th Asian Test Symposium, ATS'96 ; Conference date: 20-11-1996 Through 22-11-1996",

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T1 - Test methodology for interconnect structures of LUT-based FPGAs

AU - Michinishi, Hiroyuki

AU - Yokohira, Tokumi

AU - Okamoto, Takuji

AU - Inoue, Tomoo

AU - Fujiwara, Hideo

PY - 1996

Y1 - 1996

N2 - In this paper, we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validnesses and complexities.

AB - In this paper, we consider testing for programmable interconnect structures of look-up table based FPGAs. The interconnect structure considered in the paper consists of interconnecting wires and programmable points (switches) to join them. As fault models, stuck-at faults of the wires, and extra-device faults and missing-device faults of the programmable points are considered. We heuristically derive test procedures for the faults and then show their validnesses and complexities.

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M3 - Conference article

AN - SCOPUS:0030411716

SN - 1081-7735

SP - 68

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JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

T2 - Proceedings of the 1996 5th Asian Test Symposium, ATS'96

Y2 - 20 November 1996 through 22 November 1996

ER -

Test methodology for interconnect structures of LUT-based FPGAs

Abstract

ASJC Scopus subject areas

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