Testing for the programming circuit of LUT-based FPGAs

H. Michinishi; T. Yokohira; T. Okamoto; T. Inoue; H. Fujiwara

Testing for the programming circuit of LUT-based FPGAs

H. Michinishi, T. Yokohira, T. Okamoto, T. Inoue, H. Fujiwara

Research output: Contribution to journal › Conference article › peer-review

Abstract

The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.

Original language	English
Pages (from-to)	242-247
Number of pages	6
Journal	Proceedings of the Asian Test Symposium
Publication status	Published - 1997
Event	Proceedings of the 1997 6th Asian Test Symposium - Akita, Jpn Duration: Nov 17 1997 → Nov 19 1997

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Testing for the programming circuit of LUT-based FPGAs",

abstract = "The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.",

author = "H. Michinishi and T. Yokohira and T. Okamoto and T. Inoue and H. Fujiwara",

year = "1997",

language = "English",

pages = "242--247",

journal = "Proceedings of the Asian Test Symposium",

issn = "1081-7735",

publisher = "IEEE Computer Society",

note = "Proceedings of the 1997 6th Asian Test Symposium ; Conference date: 17-11-1997 Through 19-11-1997",

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AU - Michinishi, H.

AU - Yokohira, T.

AU - Okamoto, T.

AU - Inoue, T.

AU - Fujiwara, H.

PY - 1997

Y1 - 1997

N2 - The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.

AB - The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.

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M3 - Conference article

AN - SCOPUS:0031353808

SN - 1081-7735

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JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

T2 - Proceedings of the 1997 6th Asian Test Symposium

Y2 - 17 November 1997 through 19 November 1997

ER -

Testing for the programming circuit of LUT-based FPGAs

Abstract

ASJC Scopus subject areas

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