Very short critical path implementation of AES with direct logic gates

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)


A lot of improvements and optimizations for the hardware implementation of AES algorithm have been reported. These reports often use, instead of arithmetic operations in the AES original, those in its isomorphic tower field and. This paper focuses on which provides higher-speed arithmetic operations than. In the case of adopting, not only high-speed arithmetic operations in but also high-speed basis conversion matrices from the to should be used. Thus, this paper improves arithmetic operations in with Redundantly Represented Basis (RRB), and provides basis conversion matrices with More Miscellaneously Mixed Bases (MMMB).

Original languageEnglish
Title of host publicationAdvances in Information and Computer Security - 7th International Workshop on Security, IWSEC 2012, Proceedings
PublisherSpringer Verlag
Number of pages18
ISBN (Print)9783642341168
Publication statusPublished - 2012
Event7th International Workshop on Security, IWSEC 2012 - Fukuoka, Japan
Duration: Nov 7 2012Nov 9 2012

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume7631 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other7th International Workshop on Security, IWSEC 2012


  • AES
  • MixColumns
  • SubBytes
  • mixed bases
  • type-I optimal normal basis

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)


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