TY - GEN

T1 - Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs

AU - Abe, Koki

AU - Ishihara, Masataka

AU - Hatakenaka, Yusuke

AU - Umetani, Kazuhiro

AU - Hiraki, Eiji

N1 - Publisher Copyright:
© 2021 IEEE.

PY - 2021/6/20

Y1 - 2021/6/20

N2 - Gallium-nitride-field-effect transistors (GaN-FETs) are expected as a key component to the power density improvement of switching power converter for electric vehicles (EVs) because of their low on-resistance and fast switching capability. It is well known that the switching loss is influenced by the drain inductance, which is the parasitic inductance of the power loop, and can be minimized in principle by an appropriate design of the drain inductance. However, in switching power converters using Si-based power devices such as the Si-MOSFET and the Si-IGBT, it is usually difficult to design the drain inductance so that the switching loss minimizes because an appropriate drain inductance becomes too large, thus resulting in large surge voltages of the switching device. On the other hand, this may not be the case when using the GaN-FETs because the inductance that can minimize the switching loss may become small due to the high-di/dt switching. Therefore, the purpose of this study is to show the feasibility of the parasitic drain inductance design that the switching loss of the GaN-FET in the bridge circuit can be minimized while keeping the surge voltage of the GaN-FET within acceptable limits. The appropriateness of this insight is verified by simulation.

AB - Gallium-nitride-field-effect transistors (GaN-FETs) are expected as a key component to the power density improvement of switching power converter for electric vehicles (EVs) because of their low on-resistance and fast switching capability. It is well known that the switching loss is influenced by the drain inductance, which is the parasitic inductance of the power loop, and can be minimized in principle by an appropriate design of the drain inductance. However, in switching power converters using Si-based power devices such as the Si-MOSFET and the Si-IGBT, it is usually difficult to design the drain inductance so that the switching loss minimizes because an appropriate drain inductance becomes too large, thus resulting in large surge voltages of the switching device. On the other hand, this may not be the case when using the GaN-FETs because the inductance that can minimize the switching loss may become small due to the high-di/dt switching. Therefore, the purpose of this study is to show the feasibility of the parasitic drain inductance design that the switching loss of the GaN-FET in the bridge circuit can be minimized while keeping the surge voltage of the GaN-FET within acceptable limits. The appropriateness of this insight is verified by simulation.

KW - GaN-FET

KW - parasitic inductance

KW - power loop

KW - stray inductance

KW - switching loss

UR - http://www.scopus.com/inward/record.url?scp=85118788792&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85118788792&partnerID=8YFLogxK

U2 - 10.1109/ISIE45552.2021.9576373

DO - 10.1109/ISIE45552.2021.9576373

M3 - Conference contribution

AN - SCOPUS:85118788792

T3 - IEEE International Symposium on Industrial Electronics

BT - Proceedings of 2021 IEEE 30th International Symposium on Industrial Electronics, ISIE 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 30th IEEE International Symposium on Industrial Electronics, ISIE 2021

Y2 - 20 June 2021 through 23 June 2021

ER -