TY - GEN
T1 - MEMS interleaving read operation of a holographic memory for optically reconfigurable gate arrays
AU - Morita, Hironobu
AU - Watanabe, Minoru
N1 - Funding Information:
This research was supported by the Ministry of Education, Science, Sports and Culture, Grant-in-Aid for Scientific Research on Innovative Areas, No. 20200027. The VLSI chip in this study was fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Rohm Co. Ltd. and Toppan Printing Co. Ltd.
PY - 2011
Y1 - 2011
N2 - Optically reconfigurable gate array (ORGAs) were developed to realize next-generation large-virtual gate count programmable VLSIs. An ORGA consists of an ORGA-VLSI, a holographic memory, and a laser array, which is used for addressing the holographic memory. Since many configuration contexts can be stored on a volume-type holographic memory, the corresponding number of lasers must be implemented on an ORGA. However, a laser array with numerous lasers is always expensive. Therefore, to accommodate numerous configuration contexts with fewer lasers, this paper presents a novel method using an interleaving read operation of a holographic memory for ORGAs. This method can provide an addressing capability of a billion configuration contexts along with a nanosecond-order high-speed configuration capability.
AB - Optically reconfigurable gate array (ORGAs) were developed to realize next-generation large-virtual gate count programmable VLSIs. An ORGA consists of an ORGA-VLSI, a holographic memory, and a laser array, which is used for addressing the holographic memory. Since many configuration contexts can be stored on a volume-type holographic memory, the corresponding number of lasers must be implemented on an ORGA. However, a laser array with numerous lasers is always expensive. Therefore, to accommodate numerous configuration contexts with fewer lasers, this paper presents a novel method using an interleaving read operation of a holographic memory for ORGAs. This method can provide an addressing capability of a billion configuration contexts along with a nanosecond-order high-speed configuration capability.
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U2 - 10.1007/978-3-642-19475-7_25
DO - 10.1007/978-3-642-19475-7_25
M3 - Conference contribution
AN - SCOPUS:79953172913
SN - 9783642194740
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 242
EP - 252
BT - Reconfigurable Computing
T2 - 7th International Symposium on Applied Reconfigurable Computing, ARC 2011
Y2 - 23 March 2011 through 25 March 2011
ER -