This paper presents a neuron filter algorithm to satisfy two constraints of the graph-coloring problem through a separated board-level routing problem (s-BLRP) in an FPGA-based logic emulation system. For a rapid prototyping of large scale digital systems, multiple FPGA's provide an efficient logic emulation system, where signals or nets between design partitions embedded on different FPGA's are connected through crossbars. We propose a new neuron filter algorithm to satisfy the two constraints of the problem simultaneously. The simulation results in randomly generated benchmark size instances show that our neuron filter algorithm with the thinning out application provides the better routing capability with the shorter computation time.
|出版ステータス||Published - 1999|
|イベント||International Joint Conference on Neural Networks (IJCNN'99) - Washington, DC, USA|
継続期間: 7月 10 1999 → 7月 16 1999
|Other||International Joint Conference on Neural Networks (IJCNN'99)|
|City||Washington, DC, USA|
|Period||7/10/99 → 7/16/99|
ASJC Scopus subject areas