TY - JOUR
T1 - Performance of IEEE 802.11 Wireless LAN implemented on software defined radio with hybrid programmable architecture
AU - Shono, T.
AU - Shiba, H.
AU - Shirato, Y.
AU - Uehara, K.
AU - Araki, K.
AU - Umehira, M.
PY - 2003/7/18
Y1 - 2003/7/18
N2 - We have successfully fabricated a prototype software defined radio (SDR) transceiver that supports both Japanese PHS and IEEE 802.11 wireless LAN (WLAN). In this paper, we design an IEEE 802.11 WLAN around the SDR with its distributed and heterogeneous hybrid programmable architecture. The most difficult problem in implementing the WLAN in this way is how to meet the SIFS requirement in the IEEE 802.11 standard. This paper shows the hardware and software architecture of the prototype and how it can support the protocol processing of the IEEE 802.11 WLAN. The hybrid programmable architecture is a sophisticated combination of a general-purpose microprocessor (CPU), digital signal processors (DSPs), and programmable hardware (FPGAs). The MAC layer functions are executed on the CPU, and the PHY layer functions such as MODEM are processed by the DSP; higher-speed digital signal processes are run on the FPGA. This paper also describes an experimental evaluation of the prototype for IEEE 802.11 WLAN use.
AB - We have successfully fabricated a prototype software defined radio (SDR) transceiver that supports both Japanese PHS and IEEE 802.11 wireless LAN (WLAN). In this paper, we design an IEEE 802.11 WLAN around the SDR with its distributed and heterogeneous hybrid programmable architecture. The most difficult problem in implementing the WLAN in this way is how to meet the SIFS requirement in the IEEE 802.11 standard. This paper shows the hardware and software architecture of the prototype and how it can support the protocol processing of the IEEE 802.11 WLAN. The hybrid programmable architecture is a sophisticated combination of a general-purpose microprocessor (CPU), digital signal processors (DSPs), and programmable hardware (FPGAs). The MAC layer functions are executed on the CPU, and the PHY layer functions such as MODEM are processed by the DSP; higher-speed digital signal processes are run on the FPGA. This paper also describes an experimental evaluation of the prototype for IEEE 802.11 WLAN use.
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M3 - Conference article
AN - SCOPUS:0037632480
SN - 0536-1486
VL - 3
SP - 2035
EP - 2040
JO - IEEE International Conference on Communications
JF - IEEE International Conference on Communications
T2 - 2003 International Conference on Communications (ICC 2003)
Y2 - 11 May 2003 through 15 May 2003
ER -