TY - JOUR
T1 - Testing for the programming circuit of LUT-based FPGAs
AU - Michinishi, H.
AU - Yokohira, T.
AU - Okamoto, T.
AU - Inoue, T.
AU - Fujiwara, H.
PY - 1997
Y1 - 1997
N2 - The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.
AB - The programming circuit of look-up table based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We show that the testing can be done by using only the faculties of the programming circuit, without using additional hardware.
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M3 - Conference article
AN - SCOPUS:0031353808
SN - 1081-7735
SP - 242
EP - 247
JO - Proceedings of the Asian Test Symposium
JF - Proceedings of the Asian Test Symposium
T2 - Proceedings of the 1997 6th Asian Test Symposium
Y2 - 17 November 1997 through 19 November 1997
ER -